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is25lq 025 b is25lq 512 b is25lq 010 b is25lq 020 b is25lq 040 b 256k/512k/1m/2m/4m bit 3v quad serial flash memory with multi - i/o spi
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 2 256k/512k/1m/2m/4mbi t 3v quad serial flash memory with multi - i/o spi features ? industry standard serial interface - is25lq 040 b: 4 mbit/ 512k byte - is25lq020b: 2 mbit/ 256k byte - is25lq010b: 1 m bit/ 128k byte - is25lq512b: 512kbit/ 64kbyte - is25lq025b: 256kbit/ 32kbyte - 256 - bytes per programmable page standard - standard spi/dual/quad multi - i/o spi - supports serial flash discoverable parameters (sfdp) ? high performance serial flash (spi) - 104 mhz spi/dual/quad multi - i/o spi - 416 mhz equivalent quad spi - 52mb/s continuous data throughput - supports spi modes 0 and 3 - more than 100,000 erase/program cycles - more than 20 - year data retention ? efficient read and program modes - low instruction overhead operations - continuous data read with byte wrap around - allows xip operations (execute in place) - outperforms x16 parallel flash ? flexible & cost efficient memory architecture - uniform 4 kbyte sectors or 32/64 kbyte blocks - flexible 4, 32, 64kbyte, or chip erase - standard page program 1 to 256 bytes - program/erase suspend and resume ? low power with wide temp. ranges - sin gle 2.3v to 3.6v voltage supply - 10 ma active read current - 8 a standby current - deep power down - temp grades: extended: - 40c to +105c v grade: - 40c to +125c auto grade: - 40c to +125c ? advanced security protection - software and hardware write protection - 4x256 - byte dedicated security area with user - lockable bits, (otp) one time programmable memory - 128 bit unique id for each device ? industry standard pin - out & pb - free packages 1 - jb = 8 - pin soic 208mil - jn = 8 - pin soic 150mil - jd = 8 - pin tssop 150mil - jv = 8 - pin vvsop 150mil - jk = 8 - contact wson 6x5mm - ju = 8 - contact uson 2x3mm - kgd (call factory) note 1 : IS25LQ040B (not avail able in jd) general description the is25lq 025/512/010/020/040 b ( 256k/512k/1m/2m/4m bit) serial flash memory offers a storage solution with flexibility and performance in a simplified pin count package. issis industry standard serial interface is for systems that have limited space, pins, and power. the is25lq 025/512/010/020/040 b is ac cessed through a 4 - wire spi interface consisting of a serial data input ( si ), serial data output (so), serial clock (sck), and chip enable (ce#) pins, which also serve as multi - function i/o pins in dual and quad modes (see pin descriptions). the is25xq ser ies of flash is ideal for code shadowing to ram, execute in place (xip) operations, and storing non - volatile data. the memory array is organized into programmable pages of 256 - bytes each. the is25lq 025/512/010/020/040 b support s page program mode where 1 to 256 bytes of data can be programmed into the memory with one command. pages can be erased in groups of 4kbyte sectors, 32kbyte blocks, 64kbyte blocks, and/or the entire chip. the uniform sectors and blocks allow greater flexibility for a variety of applic ations requiring solid data retention. the device supports the standard serial peripheral interface (spi), dual/quad output (spi), and dual/quad i/o (spi). clock frequencies of up to 104mhz for all read modes allow for equivalent clock rates of up to 416mh z (104mhz x 4) allowing up to 52mbytes/s of throughput. these transfer rates can outperform 16 - bit parallel flash memories allowing for efficient memory access for a xip (execute in place) operation. the is25lq 025/512/010/020/040 b is manufactured using ind ustry leading non - volatile memory technology and offered in industry standard lead - free packages. see ordering information for the density and package combinations available.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 3 table of contents features ................................ ................................ ................................ ................................ .......................... 2 general description ................................ ................................ ................................ ................................ ... 2 1. pin configuration ................................ ................................ ................................ ................................ 5 2. pin descriptions ................................ ................................ ................................ ................................ .... 6 3. block diagram ................................ ................................ ................................ ................................ ........ 7 4. spi modes des cription ................................ ................................ ................................ ........................ 8 5. system configuration ................................ ................................ ................................ ...................... 10 5.1 block/sector addresses ................................ ................................ ................................ ........... 10 6. reg isters ................................ ................................ ................................ ................................ ............... 12 6.1. status register ................................ ................................ ................................ ............................ 12 6.2. function register ................................ ................................ ................................ ....................... 15 7. protect ion mode ................................ ................................ ................................ ................................ 16 7.1 hardware write protection ................................ ................................ ................................ .... 16 7.2 software write protection ................................ ................................ ................................ .... 16 8. device operation ................................ ................................ ................................ ................................ 17 8.1 read data operation (rd, 03h) ................................ ................................ ................................ ... 18 8.2 fast read data operation (f r, 0bh) ................................ ................................ ........................ 20 8.3 hold operation ................................ ................................ ................................ .............................. 21 8.4 fast read dual i/o operation (frdio, bbh) ................................ ................................ ............ 21 8.5 f a s t r e ad d u al o u t p u t ope r a t i o n ( f rdo, 3bh) ................................ ................................ ... 24 8.6 fast read quad output (frqo, 6bh) ................................ ................................ ........................ 26 8.7 fast read quad i/o operation (frqio, ebh) ................................ ................................ ........... 28 8.8 page program operation (pp, 02h) ................................ ................................ .......................... 30 8.9 quad input page program operation (pp q , 38h) ................................ ................................ 31 8.10 erase operation ................................ ................................ ................................ .......................... 32 8.11 secto r erase operation (ser, d7h/20h) ................................ ................................ ............... 32 8.12 block erase operation (ber32k:52h, ber64k:d8h) ................................ ............................. 33 8.13 chip erase operation (cer, c7h/60h) ................................ ................................ ..................... 34 8.14 write enable operation (wren, 06h) ................................ ................................ ..................... 35 8.15 write disable operation (wrdi, 04h) ................................ ................................ ..................... 35 8.16 read status register operation (rdsr, 05h) ................................ ................................ ... 36 8.17 write status register operation (wrsr, 01h) ................................ ................................ . 36 8.18 read function register operation (rd f r, 48h) ................................ ............................... 37 8.19 write function register operation (wr f r, 42h) ................................ ............................. 37 8.20 program/erase suspend & resume ................................ ................................ ...................... 38 8.21 deep power down (dp, b9h) ................................ ................................ ................................ ...... 39 8. 22 release deep power down (rdpd, abh) ................................ ................................ ............... 41
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 4 8.23 read product identification (rdid, abh) ................................ ................................ ............ 42 8.24 read product identification by jedec id operation (rdjdid, 9fh) ........................... 43 8.25 read device manufacturer and device id operation (rdmdid, 90h) ........................ 44 8.26 read unique id number (rduid, 4bh) ................................ ................................ ....................... 45 8.27 read sfdp operation ( rdsfdp, 5ah) ................................ ................................ ....................... 46 8.28 software reset (reset - enable (rsten , 66h ) and reset (rst , 99h ) ............................. 47 8.29 security information row (o tp area) ................................ ................................ ................ 48 8.30 information row program operation ( irp, 62h) ................................ .............................. 48 8.31 information row read operation ( irrd, 68h) ................................ ................................ ... 50 9. electrical characteristics ................................ ................................ ................................ .......... 51 9.1 absolute maximum ratings (1) ................................ ................................ ................................ .... 51 9.2 operating range ................................ ................................ ................................ ........................... 51 9.3 dc characteristics ................................ ................................ ................................ ...................... 51 9.4 ac measurement conditions ................................ ................................ ................................ .... 52 9. 5 ac characteristics ................................ ................................ ................................ ...................... 53 9.6 serial input/output timing ................................ ................................ ................................ ........ 54 9.7 power - up and power - down ................................ ................................ ................................ ...... 55 9.8 program/erase performance ................................ ................................ ................................ . 56 9.9 reliability characteristics ................................ ................................ ................................ ...... 56 10. p ackage type information ................................ ................................ ................................ ............. 57 10.1 8 - pin jedec 208mil broad small outline integrated circuit (soic) package (jb) ......................... 57 10.2 8 - pin jedec 150mil broad small outline integrated circuit (soic) package (jn) ........................ 58 10.3 8 - pin 150mil ts sop package (jd) ................................ ................................ ................................ .. 59 10.4 8 - pin 150mil v vsop package (jv) ................................ ................................ ................................ .. 60 10.5 8 - contact ultra - thin small outline no - lead (wson) package 6x5mm (jk) ................................ .. 62 10.6 8 - contact ultra - thin small outline no - lead (uson) package 2x3mm (ju) ................................ ... 63 11. ordering information ................................ ................................ ................................ ...................... 64
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 5 1. pin configuration sck vcc si (io0 ) gnd wp# (io2) so (io1) 8 - contact u son 2x3 mm (package : ju) hold# (io3) ce# 6 8 5 4 3 2 7 1 8 - pin soic 208mil (package: j b) 8 - pin soic 150mil (package: jn ) 8 - pin ts sop 150mil (package: jd) 8 - pin v v sop 150mil (package: jv) 8 - contact wson 6x5mm (package : j k ) 6 3 ce# vcc sck si (io0 ) 7 8 5 4 1 2 gnd wp# (io2) so (io1) hold# (io3) hold# (io3) vcc ce# gnd sck 1 2 3 4 7 6 5 so (io1) si (io0 ) 8 wp# (io2)
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 6 2. pin descriptions symbol type description ce# input chip enable: the chip enable (ce#) pin enables and disables the devices operation. when ce# is high the device is deselected and output pins are in a high impedance state. when deselected the devices non - critical internal circuitry power down to allow minimal levels o f power consumption while in a standby state. when ce# is pulled low the device will be selected and brought out of standby mode. the device is considered active and instructions can be written to, data read, and written to the device. after power - up, ce# must transition from high to low before a new instruction will be accepted. keeping ce# in a high state deselects the device and switches it into its low power state. data will not be accepted when ce# is high. si (io0), so (io1) input/output serial data input, serial output, and ios (si, so, io0, and io1): this device supports standard spi, dual spi, and quad spi operation. standard spi instructions use the unidirectional si (serial input) pin to write instructions, addresses, or data to the device on th e rising edge of the serial clock (sck). standard spi also uses the unidirectional so (serial output) to read data or status from the device on the falling edge of the serial clock (sck). in dual and quad spi mode, si and so become bidirectional io pins t o write instructions, addresses or data to the device on the rising edge of the serial clock (sck) and read data or status from the device on the falling edge of sck. quad spi instructions use the wp# and hold# pins as io2 and io3 respectively. wp# (io 2 ) input/output write protect/serial data io (io2): the wp# pin protects the status register from being written in conjunction with the srwd bit. when the srwd is set to 1 and the wp# is pulled low, the s tatus r egister bits (srwd, qe, bp3, bp2, bp1, bp0) are write - protected and vice - versa for wp# high. when the srwd is set to 0, the status register is not write - protected regardless of wp# state. when the qe bit is set to 1, the wp# pin (write protect) function is not available since this pin is used f or io2. hold# (io 3 ) input/output hold/serial data io (io3): pauses serial communication by the master device without resetting the serial sequence. when the qe bit of status register is set to 1, hold# pin is not available since it becomes io3. the hold# pin allows the device to be paused while it is selected. the hold# pin is active low. when hold# is in a low state, and ce# is low, the so pin will be at high impedance. device operation can resume when hold# pin is brought to a high state. when the qe bit of status register is set for quad i/o, the hold# pin function is not available and becomes io3 for multi - i/o spi mode. sck input serial data clock: synchronized clock for input and output timing operations. vcc power power: device core power supply gnd ground ground: connect to ground when referenced to vcc nc unused nc: pins labeled nc stand for no connect and should be left uncommitted.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 7 3. block diagram control logic high voltage generator i / o buffers and data latches 256 bytes page buffer y - decoder x - decoder serial peripheral interface status register address latch & counter memory array ce # sck wp # ( io 2 ) si ( io 0 ) so ( io 1 ) hold # ( io 3 )
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 8 4. spi modes description multiple is25lq 025/512/010/020/040 b devices can be connected on the spi serial bus and controlled by a spi master, i.e. micro controller, as shown in figure 4 . 1 the devices support either of two spi modes: mode 0 (0, 0) mode 3 (1, 1) the difference between these two modes is the clock polarity . w hen the spi master is in s tand - by mode , the serial clock remains at 0 (sck = 0) for mode 0 and the clock remains at 1 (sck = 1) for mode 3. please refer to figure 4 .2 for spi mode . in spi mode, the input data is latched on the rising edge of serial clock (sck), and the output data is available from the falling edge of sck. figure 4 . 1 connection diagram among spi master and spi slaves (memory devices) note s : 1. the write protect (wp#) and hold (hold#) signals should be driven high or low as necessary . 2. si and so pins become bidirectional io0 and io1, and wp# and hold# pins become io2 and io3 respectively during multi - io mode. spi interface with ( 0 , 0 ) or ( 1 , 1 ) spi master ( i . e . microcontroller ) spi memory device spi memory device spi memory device sck so si sck sdi sdo ce # wp # hold # sck so si ce # wp # hold # sck so si ce # wp # hold # cs 3 cs 2 cs 1
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 9 figure 4 . 2 spi mode support s c k s c k s o s i i n p u t m o d e m o d e 0 ( 0 , 0 ) m o d e 3 ( 1 , 1 ) m s b m s b
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 10 5. system configuration the is25lq 025/512/010/020/040 b is designed to interface directly with the synchronous serial peripheral interface (spi) microcontrollers or any spi interface - equipped system controllers. the memory array of is25lq 025/512/010/020/040 b is divided into uniform 4 kbyte sectors or uniform 32/ 64 kbyte blocks (a block consists of eight/ sixteen adjacent sectors respectively ). table 5. 1 and table 5.2 illustrate the memory map of the device. the status register controls how the memory is protected . 5.1 block/sector add resses table 5.1 block/sector addresses of is25lq025/512/010b memory density block no. (64 kbyte ) block no. (32 kbyte ) sector no. sector size ( kbyte ) address range 256 kbit 512 kbit 1 mbit block 0 block 0 sector 0 4 000000h - 000fffh sector 1 4 001000h - 001fffh : : : sector 7 4 007000h - 007fffh block 1 sector 8 4 008000h - 008fffh sector 9 4 009000h - 009fffh : : : sector 15 4 00f000h - 00ffffh block 1 block 2 sector 16 4 010000h - 010fffh sector 17 4 011000h - 011fffh : : : sector 23 4 017000h - 017fffh block 3 sector 24 4 018000h - 018fffh sector 25 4 019000h - 019fffh : : : sector 31 4 01f000h C 01ffffh
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 11 table 5. 2 block/sector addresses of is25lq 020/040 b memory density block no. (64kb yte) block no. (32kb yte) sector no. sector size (kb yte) address range 2 mbit 4 mbit block 0 block 0 sector 0 4 000000h - 000fffh : : : block 1 : : : sector 15 4 00f000h - 00ffffh block 1 block 2 sector 16 4 010000h - 010fffh : : : block 3 : : : sector 31 4 01f000h - 01ffffh block 2 block 4 sector 32 4 020000h - 020fffh : : : block 5 : : : sector 47 4 02f000h - 02ffffh block 3 block 6 sector 48 4 030000h - 030fffh : : : block 7 : : : sector 63 4 03f000h - 03ffffh block 4 block 8 sector 64 4 040000h - 040fffh : : : block 9 : : : sector 79 4 04f000h - 04ffffh block 5 block 10 sector 80 4 050000h - 050fffh : : : block 11 : : : sector 95 4 05f000h - 05ffffh block 6 block 12 sector 96 4 060000h - 060fffh : : : block 13 : : : sector 111 4 06f000h - 06ffffh block 7 block 14 sector 112 4 070000h - 070fffh : : : block 15 : : : sector 127 4 07f000h - 07ffffh
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 12 6. registers the is25lq 025/512/010/020/040 b has two sets of registers: status, function. 6.1. status register status register format and status register bit definitions are described in tables 6.1 & 6.2. table 6.1 status register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 srwd qe bp3 bp2 bp1 bp0 wel wip default 0 0 0 0 0 0 0 0 table 6.2 status register bit definition bit name definition read - /write type bit 0 wip write in progress bit: "0" indicates the device is ready (default) "1" indicates a write cycle is in progress and the device is busy r volatile bit 1 wel write enable latch: "0" indicates the device is not write enabled (default) "1" indicates the device is write enabled r volatile bit 2 bp0 block protection bit: (see tables 6. 4 for details) "0" indicates the specific blocks are not write - protected (default) "1" indicates the specific blocks are write - protected r/w non - volatile bit 3 bp1 bit 4 bp2 bit 5 bp3 bit 6 qe quad enable bit: 0 indicates the quad output function disable (default) 1 indicates the quad output function enable r/w non - volatile bit 7 srwd status register write disable: (see table 7.1 for details) "0" indicates the status register is not write - protected (default) "1" indicates the status register is write - protected r/w non - volatile the bp0, bp1, bp2, bp3 and srwd are non - volatile memory cells that can be written by a write status register (wrsr) instruction. the default value of the bp2, bp1, bp0, and srwd bits were set to 0 at factory. the status register can be read by the read status register (rdsr). the function of status register bits are described as follows: wip bit : the write in progress (wip) bit is read - only, and can be used to detect the progress o r completion of a program or erase operation. when the wip bit is 0, the device is ready for write s tatus or function r egister, program or erase operation. when the wip bit is 1, the device is busy. wel bit : the write enable latch (wel) bit indicates the status of the internal write enable latch. when the wel is 0, the write enable latch is disabled and a ll write operations described in table 6.3 are inhibited . when the wel bit is 1, write operations are allowed. the wel bit is set by a write enabl e (wren) instruction. each write register, program and erase instruction must be preceded by a wren instruction. the wel bit can be reset by a write disable (wrdi) instruction. it will automatically be reset after the completion of any write operation .
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 13 table 6.3 instructions requiring wren instruction ahead instruction s must be preceded by the wren instruction name hex code operation pp 02h input page program ppq 32h/38h quad input page program ser d7h/20h sector erase ber32 (32kb) 52h block erase 32k ber64 (64kb) d8h block erase 64k cer c7h/60h chip erase wrsr 01h write status register wrfr 42h write function register irp 62h program information row bp3, bp2, bp1, bp0 bits : the block protection ( bp3, bp2, bp1 and bp0) bits are used to define the portion of the memory area to be protected. refer to t ables 6. 4 for the block w rite protection (bp) bit settings. when a defined combination of bp3, bp2, bp1 and bp0 bits are set, the corresponding memory area is protected . any program or erase operation to that area will be inhibited. note: a chip erase (c er) instruction will be ignored unless all the block protection bits are 0s. srwd bit : the status register write disable (srwd) bit operates in conjunction with the wr ite protection (wp#) signal to provide a hardware protection mode. when the srwd is set to 0, the status register is not write - protected. when the srwd is set to 1 and the wp# is pulled low (v il ), the bits of status register (srwd, qe, bp3, bp2, bp1, bp0) become read - only, and a wrsr instruction will be ignored. if the srwd is set to 1 and wp# is pulled high (v ih ), the status register can be changed by a wrsr instruction. qe bit : the quad enable (qe) is a non - volatile bit in t he status r egister that allows q uad operation. when the qe bit is set to 0 , the pin wp# and hold# are enable d . when the qe bit is set to 1, the io2 and io3 pin s are enable d . warning: the qe bit must be set to 0 if wp# or hold# pin is tied directly to the power supply.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 14 table 6 . 4 block (64 kbyte ) assignment by block write protect (bp) bits. status register bits protected memory area bp3 bp2 bp1 bp0 4 mbit 2 mbit 1 mbit 512k and 256k 0 0 0 0 n one n one n one n one 0 0 0 1 1 block : 7 1 block : 3 1 block : 1 all blocks 0 0 1 0 2 blocks : 6 - 7 2 blocks : 2 - 3 all blocks 0 0 1 1 4 blocks : 4 - 7 all blocks 0 1 0 0 all blocks 0 1 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 0 0 1 1 0 1 0 1 0 1 1 1 1 0 0 4 blocks 0 - 3 1 1 0 1 2 blocks : 0 - 1 2 blocks : 0 - 1 1 1 1 0 1 block : 0 1 block : 0 1 block : 0 1 1 1 1 none none none none
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 15 6.2. f unction register function registe r format and bit definition are described in table 6. 5 and 6. 6. table 6 . 5 function register format bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 irl3 irl2 irl1 irl0 esus psus reserved reserved default 0 0 0 0 0 0 0 0 table 6. 6 function register bit definition bit name definition read - /write type bit 0 reserved reserved r non - volatile bit 1 reserved reserved r non - volatile bit 2 psus program suspend bit: 0 indicates program is not suspend 1 indicates program is suspend r volatile bit 3 esus erase suspend bit : "0" indicates erase is not suspend "1" indicates erase is suspend r volatile bit 4 ir lock 0 lock the information row 0: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w non - volatile bit 5 ir lock 1 lock the information row 1: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w non - volatile bit 6 ir lock 2 lock the information row 2: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w non - volatile bit 7 ir lock 3 lock the information row 3: 0 indicates the information row can be programmed 1 indicates the information row cannot be programmed r/w non - volatile note: function register bits are only o ne t ime p rogrammable (otp) and cannot be modified . psus bit : the program suspend status bit indicates when a program operation has been suspended. the psus changes to 1 after a suspend command is issued during the p rogram operation. once the suspended program resumes, the psus bit is reset to 0 . esus bit : the erase suspend status indicates when an erase operation has b een suspended. the esus bit is 1 after a suspend command is issued during an erase operation. once the suspended erase res umes, the esus bit is reset to 0 . ir lock bit 0 ~ 3 : the information row lock bit s are programmable . if the bit set to 1 , it can t be programmed.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 16 7. protection mode the is25lq 025/512/010/020/040 b supports hardware and software write - protection mecha nisms . 7.1 hardware write protection the write protection (wp#) pin provides a hardware write protection method for bp3, bp2, bp 1 , bp0 , qe, and srwd in the status register. refer to the section 6.1 status register. w rite inhibit voltage ( v wi ) is specified in the section 9.7 power - up and power - down . a ll write sequence will be ignored when vcc drops to v wi . table 7 .1 hardware write protection on status register srwd wp# status register 0 low writable 1 low protected 0 high writable 1 high writable note: before the execution of any program, erase or write status r egister instruction, the write enable latch (wel) bit must be enabled by executing a write enable (wren) instruction. if the wel bit is not enabled, the program, erase or write register instructio n will be ignored. 7.2 software write prote ction the is25lq 025/512/010/020/040 b also provides a sof tware write protection feature . the block protection ( bp3, bp2, bp1, and bp0 ) bits allow part or the whole memory area to be write - protected.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 17 8. device operation the is25lq 025/512/010/020/040 b utilizes an 8 - bit instruction register. refer to table 8 .1. instruction set for details on instructions and instruction codes. all instructions, addresses, and data are shifted in with the most significant bit (ms b ) first on serial data input (si). the input data on si is latched on the rising edge of serial clock (sck) after chip enable (ce#) is driven low (v il ). every instruction sequence starts with a one - byte instruction code and is followed by address bytes, data bytes, or both address bytes and data bytes, depending on the type of instruction. ce# must be driven high (v ih ) after the last bit of the instruction sequence has been shifted in to end the operation. table 8 . 1 instruction set inst ruction name hex code operation mode maximum frequency rd 03h read data bytes from memory at normal read mode spi 33mhz fr 0bh read data bytes from memory at fast read mode spi 104mhz frdio bbh fast read dual i/o spi 104mhz frdo 3bh fast read dual output spi 104mhz frqio ebh fast read quad i/o spi 104mhz frqo 6bh fast read quad output spi 104mhz pp 02h page program data bytes into memory spi 104mhz ppq 32h/ 38h page program data bytes into memory with quad interface spi 104mhz ser d7h/20h sector erase 4k b spi 104mhz ber32 (32 kbyte ) 52h block erase 32k b is25lq010/020/040b spi 104mhz ber64 (64 kbyte ) d8h block erase 64k b spi 104mhz ber32 (32 kbyte ) 52h/d8h block erase 32k b is25lq025 /512 b spi 104mhz ber64 (64 kbyte ) na block erase 64k b spi 104mhz cer c7h/60h chip erase spi 104mhz wren 06h write enable spi 104mhz wrdi 04h write disable spi 104mhz rdsr 05h read status register spi 104mhz wrsr 01h write status register spi 104mhz rdfr 48h read f unction r egister spi 104mhz wrfr 42h write function r egister spi 104mhz persus 75h/b0h suspend during the program/erase spi 104mhz perrsm 7ah/30h resume program/erase spi 104mhz dp b9h deep power down mode spi 104mhz rdid, rdpd abh read manufacturer and product id/release deep power down spi 104mhz rduid 4bh read unique id number spi 104mhz rdjdid 9fh read manufacturer and product id by jedec id command spi 104mhz rdmdid 90h read manufacturer and device id spi 104mhz rdsfdp 5ah sfdp read spi 104mhz rsten 66h soft ware reset enable spi 104mhz rst 99h reset spi 104mhz
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 18 instruction name hex code operation mode maximum frequency irp 62h program information row spi 104mhz irrd 68h read information row spi 104mhz 8.1 read data operation ( rd, 03 h ) the read data (rd) instruction is used to read memory contents of the is25lq 025/512/010/020/040 b at a maximum frequency of 33 mhz. the rd instruction code is transmitted via the si line, followed by three address bytes (a23 - a0) of the first memory location to be read. a total of 24 address bits are shifted in, but only a ms b (most significant bit ) - a 0 are decoded. the remaining bits (a23 C a ms b +1 ) are ignored. the first byte addre ss can be at any memory location. upon completion, any data on the si wi ll be ignored. refer to table 8 . 2 for the related address key. the fir st byte data (d7 - d0) address is shifted out on the so line, ms b first. a single byte of data, or up to the whol e memory array, can be read out in one r d instruction. the address is automatically incremented after each byte of data is shifted out. the rd operation can be terminated at any time by driving ce# high (vih) after the data comes out. when the highest addr ess of the device is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read in one continuous rd instruction. if a read data instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle . table 8 .2 address key address is25lq0 40b is25lq0 20b is25lq0 1 0 b is25lq 512b is25lq0 25b a ms b C a 0 a 18 - a0 (a23 - a 19 =x) a 17 - a0 (a23 - a 18 =x) a 16 - a0 (a23 - a 17 =x) a 15 - a0 (a23 - a 16 =x) a 14 - a0 (a23 - a 15 =x) note: x=dont care
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 19 figure 8 . 1 read data sequence 7 6 c e # s c k s i 5 3 2 s o 4 1 0 d a t a o u t 1 i n s t r u c t i o n = 0 3 h 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s h i g h i m p e d a n c e 2 2 2 1 . . . 0 1 2 3 4 5 6 7 8 9 1 0 . . . 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 m o d e 3 m o d e 0 4 8 7 6 5 3 2 4 1 0 t v d a t a o u t 2
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 20 8.2 fast read data operation ( f r, 0bh) the fast read instruction is used to read memory data at up to a 104mhz clock. the fast read instruction code is followed by three address bytes (a23 - a0) and a dummy byte (8 clocks), transmitted via the si line, with each bit latched - in during the rising edge of sck. then the first data byte from the address is shifted out on the so line, with e ach bit shifted out at a maximum frequency f ct , during the falling edge of sck. the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single fast read instruc tion. the fast read instruction is terminated by driving ce# high (vih). if a fast read instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycl e . figur e 8 .2 fast read data sequence 7 6 c e # s c k s i 5 3 2 s o 4 1 0 d a t a o u t i n s t r u c t i o n = 0 b h 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s h i g h i m p e d a n c e 2 2 2 1 . . . 0 1 2 3 4 5 6 7 8 9 1 0 . . . 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 m o d e 3 m o d e 0 4 8 . . . t v d u m m y b y t e
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 21 8.3 hold operation hold# is used in conjunction with ce# to select the is25lq 025/512/010/020/040 b . when the device is selected and a serial sequence is underway, hold# can be used to pause the serial communication with the master device without resetting the serial sequence. to pause, hold# is brought low while the sck signal is low. to resume serial communication, hold# is brought high while the sck signal is low (sck may still t oggle duri ng hold). inputs to s o will be ignored while so is in the high impedance state. timing graph can be referenced in ac parameters figure 9.3 8.4 fast read dual i/o operation ( frdio, bbh) the frdio instruction allows the address bits to be input two bits at a time. this may allow for code to be executed directly from the spi in some applications. the frdio instruction code is followed by three address bytes (a23 C a0) and a mode byte, transmitted via the io1 and io0 lines, with each pair of bits latched - in dur ing the rising edge of sck. the address msb is input on io1, the next bit on io0, and continue to shift in alternating on the two lines. if axh (x : dont care) is input for the mode byte, the device will enter ax read mode. in the ax read mode, the next in struction expected from the device will be another frdio instruction and will not need the bbh instruction code so that i t saves cycles as described in figure 8.4. if the following mode byte is not set to axh, the device will exit ax read mode. to avoid an y i/o contention problem, x should be hi - z. once address and mode byte are input the device will read out data at the specified address. the first data byte addressed is shifted out on the io1 and io0 lines, with each pair of bits shifted out at a maximum frequency f ct , during the falling edge of sck. the first bit ( msb ) is output on io1, while simultaneously the second bit is output on io0. figure 8 . 3 illustrates the timing sequence. the first byte addressed can be at any memory location. the address is automatically incremented by one after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frdio instruction. frdio instructio n is terminated by driving ce# high (v ih ). if a frdio instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 22 figure 8 . 3 fast read dual i/o seque nce (with command decode cycles) note: if the mode bits=axh (x is dont care), it can execute the ax read mode (without command) . anything but axh in the mode byte cycle will keep the same sequence . 7 5 3 7 5 1 3 1 data out 1 instruction = bb h 22 ce # sck 2 0 6 4 3 - byte address high impedance 20 18 ... 0 1 2 3 4 5 6 7 8 9 10 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 mode 3 mode 0 38 t v 23 3 1 7 5 21 19 ... io 0 io 1 3 1 2 0 6 4 2 6 4 0 2 0 7 5 3 1 6 4 2 0 ... ... ... ... ... ... ce # sck io 0 io 1 data out 2 data out 3 mode bits
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 23 figure 8 . 4 fast read dual i/o sequence (without command decode cycles) notes: 1. i f the mode bits= axh ( x: dont care), it will keep executing the ax read mode (without command). when the mode bits are different from axh (x: dont care), t he device will exit the ax read operation. 2. to avoid i/o contention, x should be hi - z. 22 ce # sck 2 0 3 - byte address 20 18 ... 0 1 2 3 ... 11 12 13 14 15 16 17 18 19 20 21 mode 3 mode 0 23 3 1 21 19 ... io 0 io 1 6 7 6 4 7 5 2 0 3 1 data out 1 t v 6 4 7 5 2 0 3 1 4 5 mode bits ... ... data out 2 2 2
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 24 8.5 f a s t r e ad d u al o u t p u t ope r a t i o n ( f rdo, 3bh) t he f rdo i n s t r u c t i o n i s u s ed to r ead m e m o r y da t a o n two o utp u t p i ns ea c h at up t o a 104mhz c l o c k . t he f rdo i n s t r u c t i o n c o d e i s f o ll o wed b y th r e e add r e s s b y tes ( a 23 C a 0) a nd a du m m y b y te ( 8 c l o c k s ) , t r an s m i tted v i a t h e io0 l i n e, w i th ea c h b i t l at c h e d - i n du ri ng t he r i s i ng edge of s c k . t hen t h e f i rs t data b y t e a dd r e ss ed is s h i ft ed o ut o n t h e io1 and io0 li n e s , w i th e a c h p a i r of b i ts s h i f ted o u t at a m a x i m u m f r equen c y f c t , du ri ng t he f a l li n g e dge of s c k . t he f i rs t b i t ( msb ) i s ou t put on io1. s i m u l ta n eou s l y the s e c ond b i t i s ou t put on i o 0 . t he f i rs t b y t e a dd r e ss ed c a n be at an y m e m o r y l o c a t i on. t he add r e s s i s au t o m at i c a l l y i n cr e m ented by one a f ter ea c h b y te of data i s s h i f ted o ut. w hen the h i g he s t add r e s s i s r ea c h ed, the a d d r e s s c ounter w i l l r o l l o v er t o the 0 00 0 00h a d d r e ss , a l l o w i ng the en t i r e m e m o r y t o be r ead w i th a s i n g l e f rdo i n s t r u c t i on. f r do i n s t r u c t i on i s te r m i nated b y d ri v i ng c e # h i gh ( vih ) . if a f rdo i n s t r u c t i on i s i ss ued wh i l e an e r a s e, p r og r am o r w r i te c y cl e i s i n p r o c e s s ( b u s y =1) the i n s t r u c t i on i s i gno r ed and w il l not ha v e any ef f e c ts on the c u rr ent c y cl e.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 25 f i gu re 8 . 5 f ast read d u a l - outpu t s e qu e n ce c e # s c k 7 5 d a t a o u t 1 i n s t r u c t i o n = 3 b h 2 3 c e # s c k 3 2 1 0 3 - b y t e a d d r e s s h i g h i m p e d a n c e 2 2 2 1 . . . 0 1 2 3 4 5 6 7 8 9 1 0 1 1 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 m o d e 3 m o d e 0 4 8 t v i o 0 i o 1 6 4 3 1 7 5 2 0 6 4 3 1 . . . 2 0 . . . d a t a o u t 2 i o 0 i o 1 8 d u m m y c y c l e s
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 26 8.6 f ast read quad output ( frqo , 6 b h) t he f r q o i n s t r u c t i on i s u s ed to r ead m e m o r y da t a o n f our output p i ns ea c h at up to a 10 4 m h z c l o c k . t he f r q o i n s t r u c t i on c ode i s f o ll o wed b y th r e e add r e s s b y tes ( a 23 C a 0) a nd a du m m y b y te ( 8 c l o c k s ) , t r an s m i tted v i a t h e s i l i n e, w i th ea c h b i t l at c h e d - i n du ri ng t he r i s i ng edge of s c k . t hen t h e f i rs t data b y t e a dd r e ss ed i s s h i ft ed o ut o n t h e i o 3, i o 2, i o 1 , and i o 0 l i ne s , w i t h ea c h g r oup of f our b i ts s h i f ted out at a m a x i m u m f r equen c y f c t , du r i n g t h e f a l l i n g e d ge of s c k . t he f i rs t b i t ( m s b ) i s out p ut o n i o 3, wh i l e s i m u l taneou s l y the s e c o nd b i t i s ou t put on i o 2, t h e th i r d b i t i s o u tput on i o 1, et c . t he f i rs t b y t e a dd r e ss ed c a n be at an y m e m o r y l o c a t i on. t he add r e s s i s au t o m at i c a l l y i n cr e m ented a f ter ea c h b y te of data i s s h i f ted o ut. w hen the h i g he s t add r e s s i s r ea c h ed, the a d d r e s s c ounter w i l l r o l l o v er t o the 0 00 0 00h a d d r e ss , a l l o w i ng the en t i r e m e m o r y t o be r ead w i th a s i n g l e f r q o i n s t r u c t i on. f r q o i n s t r u c t i on i s te r m i nated b y d ri v i ng c e # h i gh ( vih ) . if a f r qo i n s t r u c t i on i s i ss ued wh i l e an e r a s e, p r og r am o r w r i t e c y cl e i s i n p r o c e s s ( b u s y =1) the i n s t r u c t i on i s i gno r ed and w il l not ha v e any ef f e c ts on the c u rr ent c y cl e.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 27 figu r e 8. 6 fast read qu a d - output s equence ce # sck 5 1 data out 1 instruction = 6 bh 23 ce # sck 3 2 1 0 3 - byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 11 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 mode 3 mode 0 48 t v io 0 io 1 4 0 5 1 5 1 4 0 4 0 5 1 ... 4 0 ... io 0 io 1 8 dummy cycles high impedance io 2 high impedance io 3 7 3 6 2 7 3 7 3 6 2 6 2 7 3 ... 6 2 ... io 2 io 3 data out 2 data out 3 data out 4
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 28 8.7 fast read quad i/o operation ( frqio, ebh) the frqio instruction allows the address bits to be input four bits at a time. this may allow for code to be executed directly from the spi in some applications. the frqio instruction code is followed by three address bytes (a23 C a0) , a mode byte , and 4 dummy cycles , transmitted via the io3, io2, io0 and io1 lines, with each group of four bits latched - in during the rising edge of sck. the address of msb input s on io3, the next bit on io2, the next bit on io1, the next bit on io0, and continue to shift in alternating on the four. the mode byte contains the value a xh , where x is a dont care value. after four dummy clocks, t he first data byte addressed is shifted out on the io3, io2, io1 and io0 lines, with eac h group of four bits shifted out at a maximum frequency f ct , during the falling edge of sck. the first bit (msb) is output on io3, while simultaneously the second bit is output on io2, the third bit is output on io1, etc. figure 8. 7 illustrates the timing sequence. if the mode byte is axh, the ax read mode is enabled. in the mode, t he device expects that the next operation will be another frqio and subsequent fr q io execution skips command code . i t sav es command cycles as described in figure 8. 8. the device will remain in this mode until the mode byte is different from axh . the first byte addressed can be at any memory location. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allowing the entire memory to be read with a single frqio instruction. frqio instruction is terminated by driving ce# high (v ih ). if a frqio instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 29 figure 8 . 7 fast read quad i/o sequence (with command decode cycles) note: if the mode bits=axh (x is dont care), it can execute the ax read mode (without command) . anything but axh in the mode byte cycle will keep the same sequence . ce # sck 5 1 data out 1 instruction = ebh 20 ce # sck 4 0 4 0 3 - byte address high impedance 16 12 8 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 mode 3 mode 0 32 t v io 0 io 1 4 0 5 1 5 1 4 0 4 0 5 1 4 0 io 0 io 1 21 5 1 5 1 17 13 9 22 6 2 6 2 18 14 10 23 7 3 7 3 19 15 11 mode bits io 2 io 3 6 2 6 2 6 2 6 2 7 3 7 3 7 3 7 3 data out 2 data out 3 data out 4 io 2 io 3 1 0 5 1 ... 4 0 ... 2 6 2 ... 3 7 3 ... 5 4 6 7 4 dummy cycles data out 5 data out 6
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 30 8.8 pa ge program operation ( pp, 02 h ) the page program ( pp ) instruction allows up to 256 bytes data to be programmed into memory in a single operation. the destination of the memory to be programmed must be outside the protected memory area set by the block protection ( bp2, bp1, bp0) bits. the pp instruction whic h attempts to program into a page that is write - p rotected will be ignored. before the execution of pp instruction, the write enable latch (wel) must be enabled through a w rite enable (wren) instruction. the pp instruction code, three address bytes and pro gram data (1 to 256 bytes) are input via the si line. program operation will start immediately after the ce# is brought high, otherwise the pp instruction will not be executed. the internal control logic automatically handles the programming voltages and t iming. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the l ast 256 bytes are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: a program operation can alter 1s into 0s, but an erase operation is required to change 0s back to 1s. a byte cannot be reprogrammed without first erasing the whole sec tor or block. figure 8 . 8 page program sequence instruction = 0 2 h 23 ce # sck si 7 6 so 7 3 - byte address high impedance 22 ... 0 data in 1 data in 256 0 1 ... 7 8 9 ... 31 32 33 ... 39 ... 207 2 ... 20 79 mode 3 mode 0 ... 0 ... ... 0
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 31 8.9 quad input page prog ram operation ( pp q , 32h/ 38h) the quad input page program instruction allows up to 256 bytes data to be programmed into memory in a single operation with four pins (io0, io1, io2 and io3) . the destination of the memory to be programmed must be outside the protected memory area set by the block protection ( bp3, bp2, bp1, bp0) bits. a quad input page program instruction which attempts to progra m into a page that is write - protected will be ignored. before the execution of quad input page program instruction, the qe bit in the s tatus r egister must be set to 1 and the write enable latch (wel) must be enabled through a w rite enable (wren) instruct ion. the quad input page program instruction code, three address bytes and program data (1 to 256 bytes) are input via the four pins (io0, io1, io2 and io3). program operation will start immediately after the ce# is brought high, otherwise the quad input page program instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operation, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still in progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page, the previously latched data are discarded, and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of t he page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: a program operation can alter 1s into 0 s, but an erase operation is required to change 0s back to 1s. a byte cannot be reprogrammed without first erasing the whole sector or block. figure 8 . 9 quad input page program o peration i n s t r u c t i o n = 3 2 h / 3 8 h 2 3 c e # s c k 4 0 4 0 3 - b y t e a d d r e s s h i g h i m p e d a n c e 2 2 . . . 0 0 1 2 3 4 5 6 7 8 9 3 1 3 2 3 3 3 4 3 5 m o d e 3 m o d e 0 i o 0 i o 1 5 1 5 1 6 2 6 2 7 3 7 3 d a t a i n 2 i o 2 i o 3 . . . d a t a i n 1 . . . . . . . . . . . .
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 32 8.10 erase operation the memory array of the is25lq 025/512/010/020/040 b is organized into uniform 4 kbyte sectors or 32/ 64 kbyte uniform blocks (a block consists of sixteen adjacent sectors). before a byte is reprogrammed, the sector or block that contains the byte must be erased (erasing sets bits to 1). in order to erase the device, there are three erase instructions available: sector erase ( ser ), block erase ( ber) and chip erase (c er). a sector erase oper ation allows any individual sector to be erased without affecting the data in other sectors. a block erase operation erases any individual block. a chip erase operation erases the whole memory array of a device. a sector erase, block erase or chip erase op eration can be executed prior to any programming operation. 8.11 sector erase operation ( ser, d7h/20h ) a sector erase (ser) instruction erases a 4 kbyte sector . b efore the execution of a ser instruction, the write enable latch (wel) must be set via a write enab le (wren) instruction. the wel bit is reset automatically after the completion of sector an erase operation. a se r instruction is entered, after ce# is pulled low to select the device and stays low during the entire instruction sequence . the se r instructi on code, and three address bytes are input via si. erase operation will start immediately after ce# is pulled high. the internal control logic automatically handles the erase volta ge and timing. refer to figure 8 . 1 0 for the sector erase sequence. during an erase operation, all instruction will be ignored except the read status register (rdsr) instruction. the progress or completion of the erase operation can be determined by reading the wip bit in the status register using a rdsr instruction. if the wip bit is 1, the erase operation is still in progress. if the wip bit is 0, the erase operation has been completed. figure 8. 1 0 sector erase sequence instruction = d 7 h / 20 h 23 ce # sck si 3 2 so 1 0 3 - byte address high impedance 22 21 ... 0 1 2 3 4 5 6 7 8 9 10 ... 28 29 30 31 mode 3 mode 0
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 33 8.12 b lock er ase operation ( ber 32k: 52h , ber 64k: d8h ) a block erase ( b er) instruction erases a 32/ 64 kbyte block of the is25lq 025/512/010/020/040 b . before the execution of a ber instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is reset automatically after the completion of a block erase operation. the b er instruction code and three address bytes are input via si. erase operation will start immediately after the ce# is pulled high, otherwise the b er instruction will not be executed. the internal control logic automatically ha ndles the erase volta ge and timing. refer to figure 8 .1 1 - 8 .1 2 for the block erase sequence. figure 8. 1 1 block erase (64k) sequence figure 8. 1 2 block erase (32k) sequence i n s t r u c t i o n = d 8 h 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s h i g h i m p e d a n c e 2 2 2 1 . . . 0 1 2 3 4 5 6 7 8 9 1 0 . . . 2 8 2 9 3 0 3 1 m o d e 3 m o d e 0 i n s t r u c t i o n = 5 2 h 2 3 c e # s c k s i 3 2 s o 1 0 3 - b y t e a d d r e s s h i g h i m p e d a n c e 2 2 2 1 . . . 0 1 2 3 4 5 6 7 8 9 1 0 . . . 2 8 2 9 3 0 3 1 m o d e 3 m o d e 0
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 34 8.13 chip erase operation ( cer, c7h/60h ) a chip erase (c er ) instruction erases the entire memory array of a is25lq 025/512/010/020/040 b . before the execution of c er instruction, the write enable latch (wel) must be set via a write enable (wren) instruction. the wel is res et automatically after completion of a chip erase operation. the c er instruction code is input via the si. erase operation will start immediately after ce# is pulled high, otherwise the c er instruction will not be executed. the internal control logic auto matically handl es the erase voltage and timing . figure 8. 1 3 chip erase sequence instruction = c 7 h / 60 h ce # sck si 0 1 2 3 4 5 6 7 mode 3 mode 0 so high impedance
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 35 8.14 write enable operati on ( wren, 06 h ) the write enable (wren) instruction is used to set the write enable latch (wel) bit. the wel bit is reset to the write - protected state after power - up. the wel bit must be write enabled before any write operation, including sector erase, block erase, chip erase, page program, write status register, and write function register operations . the wel bit will be reset to the write - protect ed state automatically upon completion of a write operation. the wren instruction is required before any above operation is executed. figure 8 . 1 4 write enable sequence 8.15 write disable operat ion ( wrdi, 04 h ) the write disable (wrdi) instruction resets the wel bit and disables all write instructions. the wrdi instruction is not required after the execution of a write instruction, since the wel bit is autom atically reset. figure 8 . 15 write dis able sequence i n s t r u c t i o n = 0 6 h c e # s c k s i o a d d r e s s 0 1 2 3 4 5 6 7 m o d e 3 m o d e 0 s o h i g h i m p e d a n c e i n s t r u c t i o n = 0 4 h c e # s c k s i o 0 1 2 3 4 5 6 7 m o d e 3 m o d e 0 s o h i g h i m p e d a n c e
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 36 8.16 read status register operation ( rdsr, 05 h ) the read status register (rdsr) instruction provides access to the status register. during the execution of a program, erase or write s tatus r egister operation, all other instructions will be ignored except the rdsr instruction, which can be used to check the progress or completion of an operation by reading the wip bit of status register. figure 8 . 16 read status register sequence 8.17 write statu s register operation ( wrsr, 01 h ) the write status register (wrsr) instruction allows the user to enable or disable the block protection and s tatus r egister write protection features by writing 0s or 1s into the non - volatile bp3, bp2, bp1, bp0 , qe and srwd bits. figure 8 . 1 7 write status register sequence i n s t r u c t i o n = 0 5 h 7 c e # s c k s i 3 2 s o 1 0 d a t a o u t 6 5 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 m o d e 3 m o d e 0 4 t v i n s t r u c t i o n = 0 1 h c e # s c k s i s o d a t a i n 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 m o d e 3 m o d e 0 7 3 2 1 0 6 5 4 h i g h i m p e d e n c e
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 37 8.18 read function register operation ( rd f r, 48 h ) the read function register (rd f r) instruction provides access to the erase/program suspend register . during the execution of a program, erase or write s tatus r egister suspend , which can be used to check the suspend status . figure 8 . 18 read function register sequence 8.19 write function register operation ( wr f r, 42h) the write function register (wr f r) instruction allows the user to lock the information row by bit 0. (ir lock) figure 8 . 19 write function register sequence i n s t r u c t i o n = 4 8 h 7 c e # s c k s i 3 2 s o 1 0 d a t a o u t 6 5 0 1 2 3 4 5 6 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 m o d e 3 m o d e 0 4 t v instruction = 42 h ce # sck si so data in 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 mode 3 mode 0 7 3 2 1 0 6 5 4 high impedence
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 38 8.20 program/erase suspen d & resume the device allow s the interruption of sector - erase, block - erase or page - program operations to conduct other operations. 75h/ b0h command for suspend and 7ah/ 30h for resume will be used. function r egister bit2 (psus) and bit 3 (esus) are used to check whether or not the device is in suspend mode. suspend to read ready timing: 10 0 s. resu me to another suspend timing: 40 0s (recommendation) . program/erase suspen d during sector - erase or block - erase (persus 75h/ b0h) the program /erase s uspend allows the interruption of sector erase and block erase operations. after the program /e rase s uspend , wel bit will be disabled, therefore only read related, resume and reset commands can be accepted (refer to table 8.3 for more detail). to execute the program/erase suspend operation , the host drives ce# low, sends the program/erase suspend command cycle ( 75h/ b0h), then drives ce# high. the function r egister indicates that the erase has been suspended by changing the esus bit from 0 to 1 , but the device will not accept another com mand until it is ready. to determine when the device will accept a new command, poll the wip bit in the status r egister or wait the specified time t su s . when esus bit is issued, the write enable latch (wel) bit will be reset. program/erase suspen d during page programming (persus 75h/ b0h) the program /e rase s uspend allows the interruption of all program operations. after the program /e rase s uspend command, wel bit will be disabled, therefore only read related, resume and reset command s can be accepted (refer to table 8.3 for more detail). to execute the program/erase suspend operation, the host drives ce# low, sends the program/erase suspend command cycle ( 75h/ b0h), then drives ce# high. the function r egister indicates that the programming has been suspended by changing the psus bit from 0 to 1 , but the device will not accept another command until it is ready. to determine when the device will accept a new command, poll the wip bit in the status r egister or wait the specified time t su s . program/erase resume (perrsm 7a/ 30h) the program/erase resume restarts a program or erase command that was suspended, and changes the suspend status bit in the function register (esus or psus bits) back to 0 . to execute the program/erase resume operation, the host dri ves ce# low, sends the program/erase resume command cycle ( 7ah/ 30h), then drives ce# high. a cycle is two nibbles long, most significant nibble first. to determine if the internal, self - timed write operation completed, poll the wip bit in the status r egister, or wait the specified time t se , t be or t pp for sector erase, block erase, or page programming, respectively. the total write time before suspend and after resume will not exceed the uninterrupted write times t se , t be or t pp .
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 39 table 8 .3 instructi ons accepted during suspend operation suspended instruction allowed name hex code operation program or erase rd 03h read data bytes from memory at normal read mode program or erase fr 0bh read data bytes from memory at fast read mode program or erase frdio bbh fast read dual i/o program or erase frdo 3bh fast read dual output program or erase frqio ebh fast read quad i/o program or erase frqo 6bh fast read quad output program or erase rdsr 05h read status register program or erase rdfr 48h read f unction r egister program or erase perrsm 7ah/30h resume program/erase program or erase rdid abh read manufacturer and product id program or erase rduid 4bh read unique id number program or erase rdjdid 9fh read manufacturer and product id by jedec id command program or erase rdmdid 90h read manufacturer and device id program or erase rdsfdp 5ah sfdp read program or erase rsten 66h software reset enable program or erase rst 99h reset (only along with 66h) program or erase irrd 68h read information row
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 40 8.21 deep power down ( dp, b9 h ) the deep power - down (dp) instruction is for setting the device on the minimizing the power consumption (e nter into power - down mode), the standby current is reduced from i sb1 to i sb2 ). during the power - down mode, the device is not active and all write/program/erase instruction s are ignored. the instruction is initiated by driving the ce# pin low and shifting the instruction code b9h as show in the figure 8 .20 . the ce# pin must be driven high after the instruction has been latched. if this is not done the power - down will not be executed. after ce# pin driven high, the power - down state will be entered within the time duration of t dp . while in the power - down state only the release from power - down / rdid instruction, which restores the device to normal operation, will be recognized. all other instructions are ignored. this includes the read status register instruction, which is always available during normal operation. ignoring all but one instruction makes the power down state a useful condition for securing maximum write protection. it can support in spi and multi - io mode. figure 8 . 20 enter deep power down mode operation . (spi) i n s t r u c t i o n = b 9 h c e # s c k s i . . . 0 1 2 3 4 5 6 7 m o d e 3 m o d e 0 t d p
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 41 8.22 release deep power d own (rdpd, abh ) the release from power - down /read device id instruction is a multi - purpose instruction. to release the device from the power - down state mode, the instruction is issued by driving the ce# pi n low, shifting the instruction code abh and driving ce# high as shown in f igure 8 . 21. release from power - down will take the time duration of t res1 before the device will resume normal operation and other instructions are accepted. the ce# pin must remain high during the t res1 time duration. if the release from power - down / rdid instruction is issued while an erase, program or write cycle is in process (when wip equals 1) the instruction is ignored and will not have any effects on the current cycle. figure 8 . 21 release power down sequence (spi) i n s t r u c t i o n = a b h c e # s c k s i . . . 0 1 2 3 4 5 6 7 m o d e 3 m o d e 0 t r e s 1
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 42 8.23 read product identification (rdid, abh ) the release from power - down /read device id instruction is a multi - purpose instruction. it can support bot h spi and multi - io mode. the read product identification (rdid) instruction is for reading out the old style of 8 - bit electronic signature, whose values are shown as table of id definitions. the rdid instruction code is followed by three dummy bytes, each bit being latched - in on si during the rising sck edge . then the device id is shifted out on so with the msb first, each bit been shifted out during the falling edge of sck. the rdid instruction is ended by ce# go ing high. the device id for abh outputs repeatedly if additional clock cycles are continuously sen t on sck while ce# is at low. table 8 . 4 product identification manufacturer id (mf7 - mf0) issi serial flash 9dh instruction abh 90h 9fh device density device id (id7 - id0) device type + capacity (id15 - id0) 4 mb 1 2 h 401 3 h 2 mb 11 h 4012 h 1 mb 1 0 h 401 1 h 512k 05h 4010h 256k 02h 4009h figure 8 . 22 read product identification sequence i n s t r u c t i o n = a b h d e v i c e i d ( i d 7 - i d 0 ) c e # s c k s i d e v i c e i d ( i d 7 - i d 0 ) s o d a t a o u t 0 1 . . . 7 8 9 . . . 3 1 3 2 3 3 . . . 3 9 4 0 4 1 . . . 4 7 m o d e 3 m o d e 0 3 d u m m y c y l e s t v
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 43 8.24 read pro duct identification by jedec id operation (rdjdid, 9fh) the jedec id read instruction allows the user to read the manufacturer and product id of devices. refer to table 8. 4 product identification for manufacturer id and device id. after the jedec id read command (9fh) is input, the ma nufacturer id is shifted out on so with the msb first, followed by the device type and density id15 - id0 (9fh device id) ; each bit is shifted out during the falling edge of sck. if ce# stays low after the last bit of the device id is shifted out, the manufacturer id and device (type/capacity) ids will loop until ce# is pulled high . figure 8 . 2 3 read product identification by jedec id r ead sequence i n s t r u c t i o n = 9 f h m e m o r y t y p e ( i d 1 5 - i d 8 ) c e # s c k s i c a p a c i t y ( i d 7 - i d 0 ) s o d a t a o u t 0 1 . . . 7 8 9 . . . 1 5 1 6 1 7 . . . 2 3 2 4 2 5 . . . 3 1 m o d e 3 m o d e 0 m a n u f a c t u r e r i d ( m f 7 - m f 0 ) t v
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 44 8.25 read de vice manufacturer and device id operation (rdmdid, 90h) the read product identification (rdid) instruction allows the user to read the manufacturer and product id of the devices. refer to table 8. 4 product identification for manufacturer id and device id. the rdid instruction code is followed by two dummy byt es and one byte address (a7~a0), each bit being latched - in on si during the rising edge of sck. if one byte address is initially set to a0 = 0, then the manufacturer id is shifted out on so with the msb first, then the device id for 90h , with each bit bein g shifted out during the falling edge of sck. if one byte address is initially set to a0 = 1, then device id1 will be read first, followed manufacturer id. the manufacturer and device id can be read continuously alternating between the two until ce# is dri ven high . figure 8 . 2 4 read product identification by rdmdid r ead sequence note s: 1 . address a0 = 0, will output the 1 - byte manufacture id (mf7 - mf0) ? ? i n s t r u c t i o n = 9 0 h m a n u f a c t u r e r i d ( m f 7 - m f 0 ) c e # s c k s i d e v i c e i d ( i d 7 - i d 0 ) s o d a t a o u t 0 1 . . . 7 8 9 . . . 3 1 3 2 3 3 . . . 3 9 4 0 4 1 . . . 4 7 m o d e 3 m o d e 0 3 b y t e a d d r e s s t v
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 45 8.26 read unique id numbe r (rduid, 4b h) the read unique id number (rduid) instruction accesses a factory - set read - only 16 - byte number that is unique to the device. the id number can be used in conjunction with user software methods to help prevent copying or cloning of a system. the rduid ins truction is instated by driving the ce# pin low and shifting the instruction code (4bh) followed by 3 address bytes and a dummy byte. after which, the 16 - byte id is shifted out on the falling edge of sck as shown below. note: 16 - byte of data will repeat as long as ce # is low and sck is toggling. figure 8.25 read product identification sequence table 8.5 unique id addressing a[23:16] a[15:9] a[8:4] a[3:0] xxh xxh 00h 0h byte address xxh xxh 00h 1h byte address xxh xxh 00h 2h byte address xxh xxh 00h xxh xxh 00h fh byte address i n s t r u c t i o n = 4 b h d u m m y b y t e c e # s c k s i s o 0 1 . . . 7 8 9 . . . 3 1 3 2 3 3 . . . 3 9 4 0 4 1 . . . 4 7 m o d e 3 m o d e 0 3 b y t e a d d r e s s d a t a o u t t v
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 46 8.27 read sfdp operation ( rdsfdp, 5ah) the serial flash discoverable parameter (sfdp) standard provides a consistent method of describing the functional and feature capabilities of serial flash devices in a standard set of internal parameter tables. these parameter tables can be interrogated by host system software to enable adjustments needed to accommodate divergent features from multiple vendors. for more details please refer to the jedec sta ndard jesd216a (serial flash discoverable parameters). the sequence of issuing rdsfdp instruction is same as f ast read instruction : ce# goes low ? send rdsfdp instruction (5ah ) ? send 3 address bytes on si pin ? send 1 dummy byte on si pin ? read sfdp cod e on so ? to end rdsfdp operation can use ce# high at any time during data out. refer to issis application note for sfdp table. the data at the addresses that are not specified in sfdp table are undefined. figure 8 . 26 rdsfdp command ( read sfdp ) operation i n s t r u c t i o n = 5 a h d u m m y b y t e c e # s c k s i s o 0 1 . . . 7 8 9 . . . 3 1 3 2 3 3 . . . 3 9 4 0 4 1 . . . 4 7 m o d e 3 m o d e 0 3 b y t e a d d r e s s d a t a o u t t v
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 47 8.28 s oftware r eset (r eset - e nable (rsten , 66h ) and reset (rst , 99h ) the reset operation is used as a system (software) reset that puts the device in normal operating mode. this operation consists of two commands: reset - enable (rsten) and reset (rst). the reset operation requires the reset - enable command followed by the reset command. any command other than the reset command after the reset - enable command will disable the reset - enable. execute the ce# pin low ? sends the reset - enable command (66 h ), and drives ce# high. next, the host drives ce# low again, sends the reset command (99 h ), and drives c e # high. the software re set during an active program or erase operation aborts the operation, which can result in c orrupting or losing the data of the targeted address range. depending on the prior operation, the reset timing may vary. recovery from a write operation requires more latency time than recovery from other operations. note: the status and function registers remain unaffected. figure 8 . 2 7 software reset enable, software res et operation s ( rsten, 66h + rst, 99h ) instruction = 66 h ce # sck si 0 1 mode 3 mode 0 2 3 4 5 6 7 instruction = 99 h 8 9 10 11 12 13 14 15 so high impedance
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 48 8.29 security information row (otp area) the security information row is comprised of an additional 4 x 256 bytes of programmable information . the security bits can be reprogrammed by the user. any program security instruction issued while program cycle is in progress is rejected without having any effect on the cycle that is in progress. table 8 .6 information row address address assignment a [23:16] a [15:8] a[7:0] irl0 (information row lock0) 00h 00h byte address irl1 00h 10h byte address irl2 00h 20h byte address irl3 00h 30h byte address bit 7~4 of the function register is used to permanently lock the programmable memory array. - when function register bit irlx = 0 , the 256 bytes of the programmable memory array can be programmed. - when function register bit irlx = 1 , the 256 bytes of the programmable memory array function as read only . 8.30 information row prog ram operation ( irp, 62h) the information row program ( irp ) instruction allows up to 256 bytes data to be programmed into the memory in a single operation. before the execution of irp instruction, the write enable latch (wel) must be enabled through a w rite enable (wren) instruction. the i r p instruction code, three address bytes and program data (1 to 256 bytes) should be sequentially input via the si line . three address bytes has to be input as specified in the table 8.6 information row address . program operation will start once the ce# goes high, otherwise the i r p instruction will not be executed. the internal control logic automatically handles the programming voltages and timing. during a program operatio n, all instructions will be ignored except the rdsr instruction. the progress or completion of the program operation can be determined by reading the wip bit in status register via a rdsr instruction. if the wip bit is 1, the program operation is still i n progress. if wip bit is 0, the program operation has completed. if more than 256 bytes data are sent to a device, the address counter rolls over within the same page . t he previously latched data are discarded and the last 256 bytes data are kept to be programmed into the page. the starting byte can be anywhere within the page. when the end of the page is reached, the address will wrap around to the beginning of the same page. if the data to be programmed are less than a full page, the data of all other bytes on the same page will remain unchanged. note: information row is only one time p rogrammable (otp). once an information row is programmed, the data cannot be altered.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 49 figure 8 . 2 8 irp command ( information row program ) operation instruction = 6 2 h 23 ce # sck si 7 6 so 7 3 - byte address high impedance 22 ... 0 data in 1 data in 256 0 1 ... 7 8 9 ... 31 32 33 ... 39 ... 207 2 ... 20 79 mode 3 mode 0 ... 0 ... ... 0
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 50 8.31 information row read operation ( irrd, 68h) the i rrd instruction is used to read memory data at up to a 104mhz clock. the irrd instruction code is followed by three address bytes (a23 - a0) and a dummy byte (8 clocks), transmitted via the si line, with each bit latched - in during the rising edge of sck. then the first data byte addressed is shifted out on the so line, with each bi t shifted out at a maximum frequency f ct , during the falling edge of sck. the address is automatically incremented after each byte of data is shifted out. when the highest address is reached, the address counter will roll over to the 000000h address, allo wing the entire memory to be read with a single irrd instruction. the irrd instruction is terminated by driving ce# high (vih). if a irrd instruction is issued while an erase, program or write cycle is in process (wip=1) the instruction is ignored and will not have any effects on the current cycle figure 8 . 29 irrd command ( information row read ) operation i n s t r u c t i o n = 6 8 h d u m m y b y t e c e # s c k s i s o 0 1 . . . 7 8 9 . . . 3 1 3 2 3 3 . . . 3 9 4 0 4 1 . . . 4 7 m o d e 3 m o d e 0 3 b y t e a d d r e s s d a t a o u t t v
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 51 9. electrical characteristics 9 .1 absolute maximum rat ings (1) storage temperature - 6 5 o c to +1 5 0 o c surface mount lead soldering temperature standard package 240 o c 3 seconds lead - free package 260 o c 3 seconds input voltage with respect to ground on all pins - 0.5v to v cc + 0.5v all output voltage with respect to ground - 0.5v to v cc + 0.5v v cc - 0.5v to +6.0v note : 1. applied conditions greater than those listed in absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operat ional sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability . 9. 2 operating range part number is25lq 025/512/010/020/040 b operating temperature ( extended grade e ) - 4 0 c to 1 0 5 c operating temperature ( v grade: hybrid flow ) - 40c to 125c operating temperature (automotive grade a1) - 40c to 8 5c operating temperature (automotive grade a2) - 40c to 10 5c operating temperature (automotive grade a3) - 40c to 125c v cc power supply 2.3 v (v m in) C 3.6 v (vmax) ; 3.3 v (typ) 9. 3 dc characteristics (under operating range) symbol parameter condition min typ (2) max units i cc1 v cc active read current v cc = vmax at 33mhz , so = open 10 15 ma i cc2 v cc program/erase current v cc = vmax at 33mhz , so = open 1 5 3 0 ma i sb1 v cc standby current cmos v cc = v max, ce# = v cc 8 50 a i sb2 deep power down current v cc = vmax, ce# = v cc 1 5 a i li input leakage current v in = 0v to v cc 1 a i lo output leakage current v in = 0v to v cc 1 a v il (1) input low voltage - 0.5 0. 3 v cc v v ih (1) input hi gh voltage 0.7v cc v cc + 0.3 v v ol output low voltage vmin < v cc < vmax i ol = 100 a 0. 2 v v oh output high voltage i oh = - 100 a v cc - 0.2 v note s: 1. maximum dc voltage on input or i/o pins is v cc + 0.5v. during voltage transitions, input or i/o pins may overshoot v cc by + 2.0 v for a period of time not to exceed 20ns. minimum dc voltage on input or i/o pins is - 0.5v. during voltage transitions, input or i/o pins may und ershoot gnd by - 2.0 v for a period of time not to exceed 20ns. 2. typical values are included for reference only and are not guaranteed or tested. typical values are measured at v cc = v cc (typ), ta=25c
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 52 9. 4 ac m easurement c onditions symbol parameter min max units cl load capacitance 30 pf tr,tf input rise and fall times 5 ns vin input pulse voltages 0.2v cc to 0.8v cc v vrefi input timing reference voltages 0.3v cc to 0.7v cc v vrefo output timing reference voltages 0.5v cc v figure 9. 1 output test load & ac measurement i/o waveform output pin 1 . 8 k 1 . 2 k 30 pf 0 . 8 v cc 0 . 2 v cc input v cc / 2 ac measurement level
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 53 9. 5 ac characteristics (under operating range, refer to section 9. 4 for ac measurement conditions ) symbol parameter min typ max units f ct clock frequency for fast read mode 0 104 mhz f c clock frequency for read mode 0 33 mhz t ri input rise time 8 ns t fi input fall time 8 ns t ckh sck high time 4 ns t ckl sck low time 4 ns t ceh ce# high time 7 ns t cs ce# setup time 10 ns t ch ce# hold time 5 ns t ds data in setup time 2 ns t dh data in hold time 2 ns t hs hold setup time 15 ns t hd hold time 15 ns t v output valid 8 ns t oh output hold time normal mode 2 ns t dis output disable time 8 ns t hd output hold time 2 ns t hlch hold active setup time relative to sck 5 ns t chhh hold active hold time relative to sck 5 ns t hhch hold not active setup time relative to sck 5 ns t chhl hold not active hold time relative to sck 5 ns t lz hold to output low z 12 ns t hz hold to output high z 12 ns t ec sector erase time (4 kbyte ) 7 0 30 0 ms block erase time (32 kbyte ) 1 30 50 0 ms block erase time (64 kbyte ) (1) 2 00 1 0 00 ms chip erase time 256k b 0. 10 0.5 s 512kb 0.2 5 1 1mb 0 . 4 1.5 2mb 0. 7 5 2 4 mb 1 .5 3 t pp page program time extended and hybrid (e and v) 0.5 1 ms automotive grades (a1, a2, a3) 0.5 2 t vc e vcc(min) to ce# low 1 m s t res1 release deep power down 3 s t dp deep power down 3 s t w write status register time 2 10 ms t sus suspend to read ready 100 s t srst software reset cover time 100 s note 1 : 64 kbyte block erase time is not applicable to is25lq025b and is25lq512b .
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 54 9. 6 serial input/output timing figure 9. 2 serial input/output timing (1) note 1: for spi mode 0 (0,0) figure 9. 3 hold timing h i - z s o s i s c k c e # v i h v i l v i h v i l v i h v i l v o h v o l v a l i d i n t c s t c k h t c k l t d s t d h t c h t c e h t v t d i s h i - z t o h s i s o s c k c e # h o l d # t c h h l t h l c h t c h h h t h h c h t h z t l z
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 55 9. 7 power - up and power - down at power - up and power - down, the device must be not selected until vcc reaches at the right level. ( adding a simple pull - up resistor on ce# is recommended. ) power up timing symbol parameter min. max unit tvce (1) vcc(min) to ce# low 1 m s tpuw (1) power - up time delay to write instruction 1 10 ms v wi (1) write inhibit voltage 1 . 9 v note1: these parameters are characterized and are not 100% tested. v c c v c c ( m a x ) v c c ( m i n ) v ( w r i t e i n h i b i t ) r e s e t s t a t e t v c e t p u w r e a d a c c e s s a l l o w e d d e v i c e f u l l y a c c e s s i b l e c h i p s e l e c t i o n n o t a l l o w e d a l l w r i t e c o m m a n d s a r e r e j e c t e d
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 56 9. 8 program/erase perfor mance p a r ame t e r t yp m ax u n it re m a r ks s e c tor e r a s e t i m e (4kb) 70 300 m s fr o m w r i t i ng e r a s e c o m m a nd to e r a s e c o m p l et i on bl o c k e r a s e t i m e (32kb) 130 500 ms bl o c k e r a s e t i m e (64kb) 200 1000 m s ch i p e r a s e t i m e 2 56 kb 0.10 0.5 s 512kb 0.25 1 1mb 0.4 1.5 2mb 0.75 2 4mb 1.5 3 p a g e p r o g r a m m i ng t i m e extended and hybrid (e and v) 0.5 1 m s fr o m w r i t i ng p r og r am c o m m and to p r og r am c o m p l et i o n automotive grades (a1, a2, a3) 0.5 2 b y t e p r og r am 8 25 s note: these parameters are characterized and are not 100% tested. 9. 9 reliability characte ristics parameter min unit test method endurance 1 00,000 cycles jedec standard a117 data retention 20 years jedec standard a103 esd C human body model 2,000 volts jedec standard a114 esd C machine model 200 volts jedec standard a115 latch - up 100 + icc1 ma jedec standard 78 note : these parameters are characterized and are not 100% tested.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 57 10. p ackage type information 10 . 1 8 - pin jedec 208mil bro ad small outline int egrated circuit (soi c) package (jb) note : all dimensions are in millimeters.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 58 10 . 2 8 - pin jedec 150 mil broad small outl ine integrated circu it (soic) package (j n ) note: all dimensions are in millimeters.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 59 10.3 8 - pin 150mil ts sop package (jd) note: all dimensions are in millimeters.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 60 10. 4 8 - pin 150mil v vsop package (jv)
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 61
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 62 10 . 5 8 - contact ultra - thin small outline n o - lead (wson) package 6x5mm (jk) note: all dimensions are in millimeters.
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 63 10. 6 8 - contact ult ra - thin small outline n o - lead (u son) package 2x3mm (ju )
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 64 11. ordering information IS25LQ040B - jb l e temperature range e = extended ( - 40 c to +105 c) v = hybrid flow ( - 40 c to +125 c) a1 = automotive grade ( - 40 c to +85 c) a2 = automotive grade ( - 40 c to +105 c) a3 = automotive grade ( - 40 c to +125 c) packaging content l = rohs compliant package t ype jb = 8 - pin soic 208mm jn = 8 - pin soic 150mm jd = 8 - pin tssop 150mil jv = 8 - pin vvsop 150mil jk = 8 - contact wson (6x5mm) j u = 8 - contact uson (2x3 mm) jw = kgd (call factory) die revision b = revision b d ensity 040 = 4 mbit 0 20 = 2 mbit 0 10 = 1 mbit 512 = 512 k bit 025 = 256 kbit base part number is = integrated silicon solution inc. 25l q = flash, 2.3v ~ 3.6v, q uad spi
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 65 density frequency (mhz) order part number (1) package 4mb 104 IS25LQ040B - jble IS25LQ040B - jblv 8 - pin soic 208mil IS25LQ040B - jnle IS25LQ040B - jnlv 8 - pin soic 150mil IS25LQ040B - jvle IS25LQ040B - jvlv 8 - pin vvsop 150mil IS25LQ040B - jkle IS25LQ040B - jklv 8 - contact wson (6x5mm) IS25LQ040B - jule IS25LQ040B - julv 8 - contact uson (2x3mm) aec - q100 grade IS25LQ040B - jbla* 8 - pin soic 208mil IS25LQ040B - jnla* 8 - pin soic 150mil IS25LQ040B - jvla* 8 - pin vvsop 150mil IS25LQ040B - jkla* 8 - contact wson (6x5mm) IS25LQ040B - jula* 8 - contact uson (2x3mm) IS25LQ040B - jwle kgd (call factory) 2mb is25lq020b - jble is25lq020b - jblv 8 - pin soic 208mil is25lq020b - jnle is25lq020b - jnlv 8 - pin soic 150mil is25lq020b - jdle is25lq020b - jdlv 8 - pin tssop 150mil is25lq020b - jvle is25lq020b - jvlv 8 - pin vvsop 150mil is25lq020b - jkle is25lq020b - jklv 8 - contact wson (6x5mm) is25lq020b - jule is25lq020b - julv 8 - contact uson (2x3mm) aec - q100 grade is25lq020b - jbla* 8 - pin soic 208mil is25lq020b - jnla* 8 - pin soic 150mil is25lq020b - jdla* 8 - pin tssop 150mil is25lq020b - jvla* 8 - pin vvsop 150mil is25lq020b - jkla* 8 - contact wson (6x5mm) is25lq020b - jula* 8 - contact uson (2x3mm) is25lq020b - jwle kgd (call factory) 1mb is25lq010b - jble is25lq010b - jblv 8 - pin soic 208mil is25lq010b - jnle is25lq010b - jnlv 8 - pin soic 150mil is25lq010b - jdle is25lq010b - jdlv 8 - pin tssop 150mil is25lq010b - jvle is25lq010b - jvlv 8 - pin vvsop 150mil is25lq010b - jkle is25lq010b - jklv 8 - contact wson (6x5mm) is25lq010b - jule is25lq010b - julv 8 - contact uson (2x3mm) aec - q100 grade is25lq010b - jbla* 8 - pin soic 208mil is25lq010b - jnla* 8 - pin soic 150mil is25lq010b - jdla* 8 - pin tssop 150mil is25lq010b - jvla* 8 - pin vvsop 150mil is25lq010b - jkla* 8 - contact wson (6x5mm) is25lq010b - jula* 8 - contact uson (2x3mm) is25lq010b - jwle kgd (call factory)
is25 l q025/512/010/020/040b integrated silicon solution, inc. - www.issi.com rev. a 1 2 / 12 /2014 66 density frequency (mhz) order part number (1) package 512k 104 is25lq 512 b - jble is25lq 512 b - jblv 8 - pin soic 208mil is25lq 512 b - jnle is25lq 512 b - jnlv 8 - pin soic 150mil is25lq512b - jdle is25lq512b - jdlv 8 - pin tssop 150mil is25lq512b - jvle is25lq512b - jvlv 8 - pin vvsop 150mil is25lq512b - jkle is25lq512b - jklv 8 - contact wson (6x5mm) is25lq512b - jule is25lq512b - julv 8 - contact uson (2x3mm) aec - q100 grade is25lq512b - jbla* 8 - pin soic 208mil is25lq512b - jnla* 8 - pin soic 150mil is25lq512b - jdla* 8 - pin tssop 150mil is25lq512b - jvla* 8 - pin vvsop 150mil is25lq512b - jkla* 8 - contact wson (6x5mm) is25lq512b - jula* 8 - contact uson (2x3mm) is25lq512b - jwle kgd (call factory) 256k is25lq025b - jble is25lq025b - jblv 8 - pin soic 208mil is25lq025b - jnle is25lq025b - jnlv 8 - pin soic 150mil is25lq025b - jdle is25lq025b - jdlv 8 - pin tssop 150mil is25lq025b - jvle is25lq025b - jvlv 8 - pin vvsop 150mil is25lq025b - jkle is25lq025b - jklv 8 - contact wson (6x5mm) is25lq025b - jule is25lq025b - julv 8 - contact uson (2x3mm) aec - q100 grade is25lq025b - jbla* 8 - pin soic 208mil is25lq025b - jnla* 8 - pin soic 150mil is25lq025b - jdla* 8 - pin tssop 150mil is25lq025b - jvla* 8 - pin vvsop 150mil is25lq025b - jkla* 8 - contact wson (6x5mm) is25lq025b - jula* 8 - contact uson (2x3mm) is25lq025b - jwle kgd (call factory) notes: 1. contact factory for other packaging options . 2. for temp grade, e: extended grade, v: hybrid flow (non - aec - q100 devices) auto grades: a1, a2, a3 are aec - q100 devices with ppap . e = extended grade - 40 o c to 105 o c v = hybrid flow - 40 o c to 125 o c a1= auto grade 1 - 40 o c to 85 o c a2 = auto grade 2 - 40 o c to 105 o c a3 = auto grade 3 - 40 o c to 125 o c

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